---

altpll

altpll v18.1

Parameters HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit INTENDED_DEVICE_FAMILY MAX 10 WIDTH_CLOCK 5 WIDTH_PHASECOUNTERSELECT PRIMARY_CLOCK INCLK0_INPUT_FREQUENCY 20000 INCLK1_INPUT_FREQUENCY OPERATION_MODE NORMAL PLL_TYPE AUTO QUALIFY_CONF_DONE COMPENSATE_CLOCK CLK0 SCAN_CHAIN GATE_LOCK_SIGNAL GATE_LOCK_COUNTER LOCK_HIGH LOCK_LOW VALID_LOCK_MULTIPLIER INVALID_LOCK_MULTIPLIER SWITCH_OVER_ON_LOSSCLK SWITCH_OVER_ON_GATED_LOCK ENABLE_SWITCH_OVER_COUNTER SKIP_VCO SWITCH_OVER_COUNTER SWITCH_OVER_TYPE FEEDBACK_SOURCE BANDWIDTH BANDWIDTH_TYPE AUTO SPREAD_FREQUENCY DOWN_SPREAD SELF_RESET_ON_GATED_LOSS_LOCK SELF_RESET_ON_LOSS_LOCK CLK0_MULTIPLY_BY 8 CLK1_MULTIPLY_BY 8 CLK2_MULTIPLY_BY 8 CLK3_MULTIPLY_BY CLK4_MULTIPLY_BY CLK5_MULTIPLY_BY CLK6_MULTIPLY_BY CLK7_MULTIPLY_BY CLK8_MULTIPLY_BY CLK9_MULTIPLY_BY EXTCLK0_MULTIPLY_BY EXTCLK1_MULTIPLY_BY EXTCLK2_MULTIPLY_BY EXTCLK3_MULTIPLY_BY CLK0_DIVIDE_BY 5 CLK1_DIVIDE_BY 5 CLK2_DIVIDE_BY 5 CLK3_DIVIDE_BY CLK4_DIVIDE_BY CLK5_DIVIDE_BY CLK6_DIVIDE_BY CLK7_DIVIDE_BY CLK8_DIVIDE_BY CLK9_DIVIDE_BY EXTCLK0_DIVIDE_BY EXTCLK1_DIVIDE_BY EXTCLK2_DIVIDE_BY EXTCLK3_DIVIDE_BY CLK0_PHASE_SHIFT 0 CLK1_PHASE_SHIFT 7180 CLK2_PHASE_SHIFT 0 CLK3_PHASE_SHIFT CLK4_PHASE_SHIFT CLK5_PHASE_SHIFT CLK6_PHASE_SHIFT CLK7_PHASE_SHIFT CLK8_PHASE_SHIFT CLK9_PHASE_SHIFT EXTCLK0_PHASE_SHIFT EXTCLK1_PHASE_SHIFT EXTCLK2_PHASE_SHIFT EXTCLK3_PHASE_SHIFT CLK0_DUTY_CYCLE 50 CLK1_DUTY_CYCLE 50 CLK2_DUTY_CYCLE 50 CLK3_DUTY_CYCLE CLK4_DUTY_CYCLE CLK5_DUTY_CYCLE CLK6_DUTY_CYCLE CLK7_DUTY_CYCLE CLK8_DUTY_CYCLE CLK9_DUTY_CYCLE EXTCLK0_DUTY_CYCLE EXTCLK1_DUTY_CYCLE EXTCLK2_DUTY_CYCLE EXTCLK3_DUTY_CYCLE PORT_clkena0 PORT_UNUSED PORT_clkena1 PORT_UNUSED PORT_clkena2 PORT_UNUSED PORT_clkena3 PORT_UNUSED PORT_clkena4 PORT_UNUSED PORT_clkena5 PORT_UNUSED PORT_extclkena0 PORT_extclkena1 PORT_extclkena2 PORT_extclkena3 PORT_extclk0 PORT_UNUSED PORT_extclk1 PORT_UNUSED PORT_extclk2 PORT_UNUSED PORT_extclk3 PORT_UNUSED PORT_CLKBAD0 PORT_UNUSED PORT_CLKBAD1 PORT_UNUSED PORT_clk0 PORT_USED PORT_clk1 PORT_USED PORT_clk2 PORT_UNUSED PORT_clk3 PORT_UNUSED PORT_clk4 PORT_UNUSED PORT_clk5 PORT_UNUSED PORT_clk6 PORT_clk7 PORT_clk8 PORT_clk9 PORT_SCANDATA PORT_UNUSED PORT_SCANDATAOUT PORT_UNUSED PORT_SCANDONE PORT_UNUSED PORT_SCLKOUT1 PORT_SCLKOUT0 PORT_ACTIVECLOCK PORT_UNUSED PORT_CLKLOSS PORT_UNUSED PORT_INCLK1 PORT_UNUSED PORT_INCLK0 PORT_USED PORT_FBIN PORT_UNUSED PORT_PLLENA PORT_UNUSED PORT_CLKSWITCH PORT_UNUSED PORT_ARESET PORT_USED PORT_PFDENA PORT_UNUSED PORT_SCANCLK PORT_UNUSED PORT_SCANACLR PORT_UNUSED PORT_SCANREAD PORT_UNUSED PORT_SCANWRITE PORT_UNUSED PORT_ENABLE0 PORT_ENABLE1 PORT_LOCKED PORT_USED PORT_CONFIGUPDATE PORT_UNUSED PORT_FBOUT PORT_PHASEDONE PORT_UNUSED PORT_PHASESTEP PORT_UNUSED PORT_PHASEUPDOWN PORT_UNUSED PORT_SCANCLKENA PORT_UNUSED PORT_PHASECOUNTERSELECT PORT_UNUSED PORT_VCOOVERRANGE PORT_VCOUNDERRANGE DPA_MULTIPLY_BY DPA_DIVIDE_BY DPA_DIVIDER VCO_MULTIPLY_BY VCO_DIVIDE_BY SCLKOUT0_PHASE_SHIFT SCLKOUT1_PHASE_SHIFT VCO_FREQUENCY_CONTROL VCO_PHASE_SHIFT_STEP USING_FBMIMICBIDIR_PORT SCAN_CHAIN_MIF_FILE AVALON_USE_SEPARATE_SYSCLK YES HIDDEN_CONSTANTS CT#CLK2_DIVIDE_BY 5 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 8 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 8 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK YES CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 7180 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 8 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 5 CT#CLK1_DIVIDE_BY 5 CT#PORT_LOCKED PORT_USED HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK YES PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 80.00000000 PT#OUTPUT_FREQ0 80.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 7.18000000 PT#DIV_FACTOR2 5 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 5 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 80.000000 PT#EFF_OUTPUT_FREQ_VALUE1 80.000000 PT#EFF_OUTPUT_FREQ_VALUE0 80.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 8 PT#MULT_FACTOR1 8 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1431678311686067.mif PT#ACTIVECLK_CHECK 0 HIDDEN_USED_PORTS UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 HIDDEN_IF_PORTS IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#inclk0 {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} HIDDEN_IS_FIRST_EDIT 0 AUTO_DEVICE_FAMILY MAX10FPGA AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000 deviceFamily MAX 10 generateLegacySim false

  

Software Assignments (none)

---

clk_0

clock_source v18.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

flash

altera_generic_tristate_controller v18.1

Parameters TCM_ADDRESS_W 22 TCM_DATA_W 16 TCM_BYTEENABLE_W 2 TCM_READ_WAIT 100 TCM_WRITE_WAIT 100 TCM_SETUP_WAIT 25 TCM_DATA_HOLD 20 TCM_MAX_PENDING_READ_TRANSACTIONS 3 TCM_TURNAROUND_TIME 2 TCM_TIMING_UNITS 0 TCM_READLATENCY 2 TCM_SYMBOLS_PER_WORD 2 USE_READDATA 1 USE_WRITEDATA 1 USE_READ 1 USE_WRITE 1 USE_BEGINTRANSFER 0 USE_BYTEENABLE 0 USE_CHIPSELECT 1 USE_LOCK 0 USE_ADDRESS 1 USE_WAITREQUEST 0 USE_WRITEBYTEENABLE 0 USE_OUTPUTENABLE 0 USE_RESETREQUEST 0 USE_IRQ 0 USE_RESET_OUTPUT 1 ACTIVE_LOW_READ 1 ACTIVE_LOW_LOCK 0 ACTIVE_LOW_WRITE 1 ACTIVE_LOW_CHIPSELECT 1 ACTIVE_LOW_BYTEENABLE 0 ACTIVE_LOW_OUTPUTENABLE 0 ACTIVE_LOW_WRITEBYTEENABLE 0 ACTIVE_LOW_WAITREQUEST 0 ACTIVE_LOW_BEGINTRANSFER 0 ACTIVE_LOW_RESETREQUEST 0 ACTIVE_LOW_IRQ 0 ACTIVE_LOW_RESET_OUTPUT 1 CHIPSELECT_THROUGH_READLATENCY 0 IS_MEMORY_DEVICE 1 MODULE_ASSIGNMENT_KEYS embeddedsw.configuration.hwClassnameDriverSupportDefault,embeddedsw.CMacro.SETUP_VALUE,embeddedsw.CMacro.WAIT_VALUE,embeddedsw.CMacro.HOLD_VALUE,embeddedsw.CMacro.TIMING_UNITS,embeddedsw.CMacro.SIZE,embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH,embeddedsw.memoryInfo.HAS_BYTE_LANE,embeddedsw.memoryInfo.IS_FLASH,embeddedsw.memoryInfo.GENERATE_DAT_SYM,embeddedsw.memoryInfo.GENERATE_FLASH,embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR,embeddedsw.memoryInfo.FLASH_INSTALL_DIR MODULE_ASSIGNMENT_VALUES altera_avalon_cfi_flash,0,0,0,ns,262144u,16,0,1,1,1,SIM_DIR,APP_DIR INTERFACE_ASSIGNMENT_KEYS embeddedsw.configuration.isFlash,embeddedsw.configuration.isMemoryDevice,embeddedsw.configuration.isNonVolatileStorage INTERFACE_ASSIGNMENT_VALUES 1,1,1 CLOCK_RATE 80000000 AUTO_DEVICE_FAMILY MAX10FPGA AUTO_DEVICE 10M08SCU169I7G AUTO_DEVICE_SPEEDGRADE 7 AUTO_CLK_CLOCK_DOMAIN 1 AUTO_CLK_RESET_DOMAIN 1 deviceFamily MAX 10 generateLegacySim false

  

Software Assignments HOLD_VALUE 0 SETUP_VALUE 0 SIZE 262144u TIMING_UNITS ns WAIT_VALUE 0

---

jtag_uart_0

altera_avalon_jtag_uart v18.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions NO_INTERACTIVE_WINDOWS useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 clkFreq 80000000 avalonSpec 2.0 legacySignalAllow false enableInteractiveInput false enableInteractiveOutput false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments READ_DEPTH 64 READ_THRESHOLD 8 WRITE_DEPTH 64 WRITE_THRESHOLD 8

---

nios2_gen2

altera_nios2_gen2 v18.1

Parameters tmr_enabled false setting_disable_tmr_inj false setting_showUnpublishedSettings false setting_showInternalSettings false setting_preciseIllegalMemAccessException false setting_exportPCB false setting_exportdebuginfo false setting_clearXBitsLDNonBypass true setting_bigEndian false setting_export_large_RAMs false setting_asic_enabled false register_file_por false setting_asic_synopsys_translate_on_off false setting_asic_third_party_synthesis false setting_asic_add_scan_mode_input false setting_oci_version 1 setting_fast_register_read false setting_exportHostDebugPort false setting_oci_export_jtag_signals false setting_avalonDebugPortPresent false setting_alwaysEncrypt true io_regionbase 0 io_regionsize 0 setting_support31bitdcachebypass true setting_activateTrace false setting_allow_break_inst false setting_activateTestEndChecker false setting_ecc_sim_test_ports false setting_disableocitrace false setting_activateMonitors true setting_HDLSimCachesCleared true setting_HBreakTest false setting_breakslaveoveride false mpu_useLimit false mpu_enabled false mmu_enabled false mmu_autoAssignTlbPtrSz true cpuReset false resetrequest_enabled true setting_removeRAMinit false setting_tmr_output_disable false setting_shadowRegisterSets 0 mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mmu_TLBMissExcOffset 0 resetOffset 0 exceptionOffset 32 cpuID 0 breakOffset 32 userDefinedSettings tracefilename resetSlave flash.uas mmu_TLBMissExcSlave None exceptionSlave onchip_memory.s1 breakSlave None setting_interruptControllerType Internal setting_branchpredictiontype Dynamic setting_bhtPtrSz 8 cpuArchRev 1 stratix_dspblock_shift_mul false shifterType medium_le_shift multiplierType no_mul mul_shift_choice 0 mul_32_impl 2 mul_64_impl 0 shift_rot_impl 1 dividerType no_div mpu_minInstRegionSize 12 mpu_minDataRegionSize 12 mmu_uitlbNumEntries 4 mmu_udtlbNumEntries 6 mmu_tlbPtrSz 7 mmu_tlbNumWays 16 mmu_processIDNumBits 8 impl Tiny icache_size 4096 fa_cache_line 2 fa_cache_linesize 0 icache_tagramBlockType Automatic icache_ramBlockType Automatic icache_numTCIM 0 icache_burstType None dcache_bursts false dcache_victim_buf_impl ram dcache_size 2048 dcache_tagramBlockType Automatic dcache_ramBlockType Automatic dcache_numTCDM 0 setting_exportvectors false setting_usedesignware false setting_ecc_present false setting_ic_ecc_present true setting_rf_ecc_present true setting_mmu_ecc_present true setting_dc_ecc_present true setting_itcm_ecc_present true setting_dtcm_ecc_present true regfile_ramBlockType Automatic ocimem_ramBlockType Automatic ocimem_ramInit false mmu_ramBlockType Automatic bht_ramBlockType Automatic cdx_enabled false mpx_enabled false debug_enabled true debug_triggerArming true debug_debugReqSignals false debug_assignJtagInstanceID false debug_jtagInstanceID 0 debug_OCIOnchipTrace _128 debug_hwbreakpoint 0 debug_datatrigger 0 debug_traceType none debug_traceStorage onchip_trace master_addr_map false instruction_master_paddr_base 0 instruction_master_paddr_size 0 flash_instruction_master_paddr_base 0 flash_instruction_master_paddr_size 0 data_master_paddr_base 0 data_master_paddr_size 0 tightly_coupled_instruction_master_0_paddr_base 0 tightly_coupled_instruction_master_0_paddr_size 0 tightly_coupled_instruction_master_1_paddr_base 0 tightly_coupled_instruction_master_1_paddr_size 0 tightly_coupled_instruction_master_2_paddr_base 0 tightly_coupled_instruction_master_2_paddr_size 0 tightly_coupled_instruction_master_3_paddr_base 0 tightly_coupled_instruction_master_3_paddr_size 0 tightly_coupled_data_master_0_paddr_base 0 tightly_coupled_data_master_0_paddr_size 0 tightly_coupled_data_master_1_paddr_base 0 tightly_coupled_data_master_1_paddr_size 0 tightly_coupled_data_master_2_paddr_base 0 tightly_coupled_data_master_2_paddr_size 0 tightly_coupled_data_master_3_paddr_base 0 tightly_coupled_data_master_3_paddr_size 0 instruction_master_high_performance_paddr_base 0 instruction_master_high_performance_paddr_size 0 data_master_high_performance_paddr_base 0 data_master_high_performance_paddr_size 0 resetAbsoluteAddr 33554432 exceptionAbsoluteAddr 1048608 breakAbsoluteAddr 2099232 mmu_TLBMissExcAbsAddr 0 dcache_bursts_derived false dcache_size_derived 2048 breakSlave_derived nios2_gen2.debug_mem_slave dcache_lineSize_derived 32 setting_ioregionBypassDCache false setting_bit31BypassDCache false translate_on "synthesis translate_on" translate_off "synthesis translate_off" debug_onchiptrace false debug_offchiptrace false debug_insttrace false debug_datatrace false instAddrWidth 26 faAddrWidth 1 dataAddrWidth 26 tightlyCoupledDataMaster0AddrWidth 1 tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster3AddrWidth 1 dataMasterHighPerformanceAddrWidth 1 instructionMasterHighPerformanceAddrWidth 1 instSlaveMapParam <address-map><slave name='onchip_flash.data' start='0x0' end='0x8000' type='altera_onchip_flash.data' /><slave name='onchip_memory.s1' start='0x100000' end='0x104000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x200800' end='0x201000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sdram.s1' start='0x1000000' end='0x1800000' type='altera_sdram_tri_controller.s1' /><slave name='flash.uas' start='0x2000000' end='0x2400000' type='altera_generic_tristate_controller.uas' /></address-map> faSlaveMapParam dataSlaveMapParam <address-map><slave name='onchip_flash.data' start='0x0' end='0x8000' type='altera_onchip_flash.data' /><slave name='onchip_memory.s1' start='0x100000' end='0x104000' type='altera_avalon_onchip_memory2.s1' /><slave name='pio_led.s1' start='0x200100' end='0x200110' type='altera_avalon_pio.s1' /><slave name='timer_100ms.s1' start='0x200180' end='0x2001A0' type='altera_avalon_timer.s1' /><slave name='altpll.pll_slave' start='0x2001C0' end='0x2001D0' type='altpll.pll_slave' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2001E0' end='0x2001E8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sysid_qsys.control_slave' start='0x200200' end='0x200208' type='altera_avalon_sysid_qsys.control_slave' /><slave name='nios2_gen2.debug_mem_slave' start='0x200800' end='0x201000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='uart_0.s1' start='0x201000' end='0x201020' type='altera_avalon_uart.s1' /><slave name='sdram.s1' start='0x1000000' end='0x1800000' type='altera_sdram_tri_controller.s1' /><slave name='flash.uas' start='0x2000000' end='0x2400000' type='altera_generic_tristate_controller.uas' /></address-map> tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster3MapParam tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster3MapParam dataMasterHighPerformanceMapParam instructionMasterHighPerformanceMapParam clockFrequency 80000000 deviceFamilyName MAX10FPGA internalIrqMaskSystemInfo 7 customInstSlavesSystemInfo <info/> customInstSlavesSystemInfo_nios_a <info/> customInstSlavesSystemInfo_nios_b <info/> customInstSlavesSystemInfo_nios_c <info/> deviceFeaturesSystemInfo ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 AUTO_DEVICE 10M08SCU169I7G AUTO_DEVICE_SPEEDGRADE 7 AUTO_CLK_CLOCK_DOMAIN 1 AUTO_CLK_RESET_DOMAIN 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIG_ENDIAN 0 BREAK_ADDR 0x00200820 CPU_ARCH_NIOS2_R1 CPU_FREQ 80000000u CPU_ID_SIZE 1 CPU_ID_VALUE 0x00000000 CPU_IMPLEMENTATION "tiny" DATA_ADDR_WIDTH 26 DCACHE_LINE_SIZE 0 DCACHE_LINE_SIZE_LOG2 0 DCACHE_SIZE 0 EXCEPTION_ADDR 0x00100020 FLASH_ACCELERATOR_LINES 0 FLASH_ACCELERATOR_LINE_SIZE 0 FLUSHDA_SUPPORTED HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 0 HARDWARE_MULX_PRESENT 0 HAS_DEBUG_CORE 1 HAS_DEBUG_STUB HAS_ILLEGAL_INSTRUCTION_EXCEPTION HAS_JMPI_INSTRUCTION ICACHE_LINE_SIZE 0 ICACHE_LINE_SIZE_LOG2 0 ICACHE_SIZE 0 INST_ADDR_WIDTH 26 OCI_VERSION 1 RESET_ADDR 0x02000000

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onchip_flash

altera_onchip_flash v18.1

Parameters DATA_INTERFACE Parallel READ_BURST_MODE Incrementing READ_BURST_COUNT 8 CLOCK_FREQUENCY 80.0 CONFIGURATION_SCHEME Internal Configuration CONFIGURATION_MODE Single Uncompressed Image SECTOR_ID 1,2,NA,NA,NA SECTOR_ACCESS_MODE Read only,Read only,Hidden,Hidden,Hidden SECTOR_ADDRESS_MAPPING 0x00000 - 0x03fff,0x04000 - 0x07fff,NA,NA,NA SECTOR_STORAGE_TYPE UFM,UFM,NA,CFM,CFM initFlashContent false useNonDefaultInitFile false initializationFileName altera_onchip_flash.hex initializationFileNameForSim altera_onchip_flash.dat autoInitializationFileName keim08core_onchip_flash INIT_FILENAME INIT_FILENAME_SIM DEVICE_FAMILY MAX10FPGA PART_NAME 10M08SCU169I7G AUTO_CLOCK_RATE 80000000 DEVICE_ID 08 SECTOR1_START_ADDR 0 SECTOR1_END_ADDR 4095 SECTOR2_START_ADDR 4096 SECTOR2_END_ADDR 8191 SECTOR3_START_ADDR 0 SECTOR3_END_ADDR 0 SECTOR4_START_ADDR 0 SECTOR4_END_ADDR 0 SECTOR5_START_ADDR 0 SECTOR5_END_ADDR 0 MIN_VALID_ADDR 0 MAX_VALID_ADDR 8191 MIN_UFM_VALID_ADDR 0 MAX_UFM_VALID_ADDR 8191 SECTOR1_MAP 1 SECTOR2_MAP 2 SECTOR3_MAP 0 SECTOR4_MAP 0 SECTOR5_MAP 0 ADDR_RANGE1_END_ADDR 8191 ADDR_RANGE2_END_ADDR 8191 ADDR_RANGE1_OFFSET 512 ADDR_RANGE2_OFFSET 0 ADDR_RANGE3_OFFSET 0 AVMM_DATA_ADDR_WIDTH 13 AVMM_DATA_DATA_WIDTH 32 AVMM_DATA_BURSTCOUNT_WIDTH 4 SECTOR_READ_PROTECTION_MODE 31 FLASH_SEQ_READ_DATA_COUNT 2 FLASH_ADDR_ALIGNMENT_BITS 1 FLASH_READ_CYCLE_MAX_INDEX 4 FLASH_RESET_CYCLE_MAX_INDEX 20 FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX 96 FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX 28000000 FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX 24400 PARALLEL_MODE true READ_AND_WRITE_MODE false WRAPPING_BURST_MODE false IS_DUAL_BOOT False IS_ERAM_SKIP True IS_COMPRESSED_IMAGE False deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BYTES_PER_PAGE 2048 READ_ONLY_MODE 1 SECTOR1_ENABLED 1 SECTOR1_END_ADDR 16383 SECTOR1_START_ADDR 0 SECTOR2_ENABLED 1 SECTOR2_END_ADDR 32767 SECTOR2_START_ADDR 16384 SECTOR3_ENABLED 0 SECTOR3_END_ADDR -1 SECTOR3_START_ADDR -1 SECTOR4_ENABLED 0 SECTOR4_END_ADDR -1 SECTOR4_START_ADDR -1 SECTOR5_ENABLED 0 SECTOR5_END_ADDR -1 SECTOR5_START_ADDR -1

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onchip_memory

altera_avalon_onchip_memory2 v18.1

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 dataWidth2 32 dualPort false enableDiffWidth false derived_enableDiffWidth false initMemContent false initializationFileName onchip_mem.hex enPRInitMode false instanceID NONE memorySize 16384 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false simMemInitOnlyFilename 0 singleClockOperation false derived_singleClockOperation false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false copyInitFile false useShallowMemBlocks false writable true ecc_enabled false resetrequest_enabled true autoInitializationFileName keim08core_onchip_memory deviceFamily MAX10FPGA deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 derived_set_addr_width 12 derived_set_addr_width2 12 derived_set_data_width 32 derived_set_data_width2 32 derived_gui_ram_block_type Automatic derived_is_hardcopy false derived_init_file_name keim08core_onchip_memory.hex generateLegacySim false

  

Software Assignments ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 CONTENTS_INFO "" DUAL_PORT 0 GUI_RAM_BLOCK_TYPE AUTO INIT_CONTENTS_FILE keim08core_onchip_memory INIT_MEM_CONTENT 0 INSTANCE_ID NONE NON_DEFAULT_INIT_FILE_ENABLED 0 RAM_BLOCK_TYPE AUTO READ_DURING_WRITE_MODE DONT_CARE SINGLE_CLOCK_OP 0 SIZE_MULTIPLE 1 SIZE_VALUE 16384 WRITABLE 1

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pio_led

altera_avalon_pio v18.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 2 clockRate 80000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 2 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 80000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

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reset_controller

altera_reset_controller v18.1

Parameters NUM_RESET_INPUTS 2 OUTPUT_RESET_SYNC_EDGES deassert SYNC_DEPTH 2 RESET_REQUEST_PRESENT 0 RESET_REQ_WAIT_TIME 1 MIN_RST_ASSERTION_TIME 3 RESET_REQ_EARLY_DSRT_TIME 1 USE_RESET_REQUEST_IN0 0 USE_RESET_REQUEST_IN1 0 USE_RESET_REQUEST_IN2 0 USE_RESET_REQUEST_IN3 0 USE_RESET_REQUEST_IN4 0 USE_RESET_REQUEST_IN5 0 USE_RESET_REQUEST_IN6 0 USE_RESET_REQUEST_IN7 0 USE_RESET_REQUEST_IN8 0 USE_RESET_REQUEST_IN9 0 USE_RESET_REQUEST_IN10 0 USE_RESET_REQUEST_IN11 0 USE_RESET_REQUEST_IN12 0 USE_RESET_REQUEST_IN13 0 USE_RESET_REQUEST_IN14 0 USE_RESET_REQUEST_IN15 0 USE_RESET_REQUEST_INPUT 0 ADAPT_RESET_REQUEST 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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sdram

altera_sdram_tri_controller v18.1

Parameters TAC 5.5 TRCD 20.0 TRFC 70.0 TRP 20.0 TWR 14.0 CAS_LATENCY 3 SDRAM_COL_WIDTH 8 SDRAM_DATA_WIDTH 16 generateSimulationModel true INIT_REFRESH 2 model single_Micron_MT48LC4M32B2_7_chip numberOfBanks 4 NUM_CHIPSELECTS 1 TRISTATE_EN true powerUpDelay 0.0 refreshPeriod 15.625 SDRAM_ROW_WIDTH 12 clockRate 80000000 componentName keim08core_sdram T_RCD 1 T_RFC 5 T_RP 1 T_WR 1 SDRAM_BANK_WIDTH 2 POWERUP_DELAY 0 REFRESH_PERIOD 1250 size 8388608 CNTRL_ADDR_WIDTH 22 MAX_REC_TIME 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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sysid_qsys

altera_avalon_sysid_qsys v18.1

Parameters id 0 timestamp 1540190710 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ID 0 TIMESTAMP 1540190710

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timer_100ms

altera_avalon_timer v18.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 100 periodUnits MSEC resetOutput false snapshot true timeoutPulseOutput false systemFrequency 80000000 watchdogPulse 2 timerPreset FULL_FEATURED periodUnitsString ms valueInSecond 0.001 loadValue 7999999 mult 0.001 ticksPerSec 10.0 slave_address_width 3 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 COUNTER_SIZE 32 FIXED_PERIOD 0 FREQ 80000000 LOAD_VALUE 7999999 MULT 0.001 PERIOD 100 PERIOD_UNITS ms RESET_OUTPUT 0 SNAPSHOT 1 TICKS_PER_SEC 10 TIMEOUT_PULSE_OUTPUT 0

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tristate_conduit_bridge_0

altera_tristate_conduit_bridge v18.1

Parameters INTERFACE_INFO <info><slave name="tcs"><master name="tristate_conduit_pin_sharer_0.tcm"><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="flash_tcm_read_n_out" width="1" type="Output" output_name="flash_tcm_read_n_out" output_enable_name="" input_name="" /><pin role="flash_tcm_reset_n_out" width="1" type="Output" output_name="flash_tcm_reset_n_out" output_enable_name="" input_name="" /><pin role="flash_tcm_write_n_out" width="1" type="Output" output_name="flash_tcm_write_n_out" output_enable_name="" input_name="" /><pin role="flash_tcm_chipselect_n_out" width="1" type="Output" output_name="flash_tcm_chipselect_n_out" output_enable_name="" input_name="" /><pin role="sdram_sdram_ras_n" width="1" type="Output" output_name="sdram_sdram_ras_n" output_enable_name="" input_name="" /><pin role="sdram_sdram_we_n" width="1" type="Output" output_name="sdram_sdram_we_n" output_enable_name="" input_name="" /><pin role="sdram_sdram_cs_n" width="1" type="Output" output_name="sdram_sdram_cs_n" output_enable_name="" input_name="" /><pin role="sdram_sdram_ba" width="2" type="Output" output_name="sdram_sdram_ba" output_enable_name="" input_name="" /><pin role="sdram_sdram_dqm" width="2" type="Output" output_name="sdram_sdram_dqm" output_enable_name="" input_name="" /><pin role="sdram_sdram_cas_n" width="1" type="Output" output_name="sdram_sdram_cas_n" output_enable_name="" input_name="" /><pin role="sdram_sdram_cke" width="1" type="Output" output_name="sdram_sdram_cke" output_enable_name="" input_name="" /><pin role="dq" width="16" type="Bidirectional" output_name="dq" output_enable_name="dq_outen" input_name="dq_in" /><pin role="addr" width="22" type="Output" output_name="addr" output_enable_name="" input_name="" /></master></slave></info> deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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tristate_conduit_pin_sharer_0

altera_tristate_conduit_pin_sharer v18.1

Parameters INTERFACE_INFO <info><slave name="tcs0"><master name="sdram.tcm"><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="dq" width="16" type="Bidirectional" output_name="sdram_dq_out" output_enable_name="sdram_dq_oe" input_name="sdram_dq_in" /><pin role="addr" width="12" type="Output" output_name="sdram_addr" output_enable_name="" input_name="" /><pin role="ba" width="2" type="Output" output_name="sdram_ba" output_enable_name="" input_name="" /><pin role="cas" width="1" type="Output" output_name="sdram_cas_n" output_enable_name="" input_name="" /><pin role="cke" width="1" type="Output" output_name="sdram_cke" output_enable_name="" input_name="" /><pin role="cs" width="1" type="Output" output_name="sdram_cs_n" output_enable_name="" input_name="" /><pin role="dqm" width="2" type="Output" output_name="sdram_dqm" output_enable_name="" input_name="" /><pin role="ras" width="1" type="Output" output_name="sdram_ras_n" output_enable_name="" input_name="" /><pin role="we" width="1" type="Output" output_name="sdram_we_n" output_enable_name="" input_name="" /></master></slave><slave name="tcs1"><master name="flash.tcm"><pin role="write_n" width="1" type="Output" output_name="tcm_write_n_out" output_enable_name="" input_name="" /><pin role="read_n" width="1" type="Output" output_name="tcm_read_n_out" output_enable_name="" input_name="" /><pin role="chipselect_n" width="1" type="Output" output_name="tcm_chipselect_n_out" output_enable_name="" input_name="" /><pin role="reset_n" width="1" type="Output" output_name="tcm_reset_n_out" output_enable_name="" input_name="" /><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="address" width="22" type="Output" output_name="tcm_address_out" output_enable_name="" input_name="" /><pin role="data" width="16" type="Bidirectional" output_name="tcm_data_out" output_enable_name="tcm_data_outen" input_name="tcm_data_in" /></master></slave></info> NUM_INTERFACES 2 MODULE_ORIGIN_LIST flash.tcm,flash.tcm,flash.tcm,flash.tcm,flash.tcm,flash.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm SIGNAL_ORIGIN_LIST address,read_n,reset_n,write_n,data,chipselect_n,ras,we,dq,cs,addr,ba,dqm,cas,cke SIGNAL_ORIGIN_TYPE Output,Output,Output,Output,Bidirectional,Output,Output,Output,Bidirectional,Output,Output,Output,Output,Output,Output SIGNAL_ORIGIN_WIDTH 22,1,1,1,16,1,1,1,16,1,12,2,2,1,1 SHARED_SIGNAL_LIST addr,,,,dq,,,,dq,,addr, SIGNAL_OUTPUT_NAMES tcm_address_out,tcm_read_n_out,tcm_reset_n_out,tcm_write_n_out,tcm_data_out,tcm_chipselect_n_out,sdram_ras_n,sdram_we_n,sdram_dq_out,sdram_cs_n,sdram_addr,sdram_ba,sdram_dqm,sdram_cas_n,sdram_cke SIGNAL_INPUT_NAMES ,,,,tcm_data_in,,,,sdram_dq_in,,,, SIGNAL_OUTPUT_ENABLE_NAMES ,,,,tcm_data_outen,,,,sdram_dq_oe,,,, REALTIME_MODULE_ORIGIN_LIST flash.tcm,flash.tcm,flash.tcm,flash.tcm,flash.tcm,flash.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm,sdram.tcm REALTIME_SIGNAL_ORIGIN_LIST address,read_n,reset_n,write_n,data,chipselect_n,ras,we,dq,cs,addr,ba,dqm,cas,cke REALTIME_SHARED_SIGNAL_LIST addr,,,,dq,,,,dq,,addr,, AUTO_DEVICE_FAMILY MAX10FPGA AUTO_DEVICE 10M08SCU169I7G AUTO_DEVICE_SPEEDGRADE 7 AUTO_CLK_CLOCK_RATE 80000000 AUTO_CLK_CLOCK_DOMAIN 1 AUTO_CLK_RESET_DOMAIN 1 deviceFamily MAX 10 generateLegacySim false

  

Software Assignments (none)

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uart_0

altera_avalon_uart v18.1

Parameters baud 115200 dataBits 8 fixedBaud false parity NONE simCharStream simInteractiveInputEnable false simInteractiveOutputEnable false simTrueBaud false stopBits 1 syncRegDepth 2 useCtsRts false useEopRegister false useRelativePathForSimFile false clockRate 80000000 baudError 0.0 parityFisrtChar N deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BAUD 115200 DATA_BITS 8 FIXED_BAUD 0 FREQ 80000000 PARITY 'N' SIM_CHAR_STREAM "" SIM_TRUE_BAUD 0 STOP_BITS 1 SYNC_REG_DEPTH 2 USE_CTS_RTS 0 USE_EOP_REGISTER 0